Hybrid architecture for multiple transforms for signal processing applications Shikha Tripathi.
Chaithanya Krishna, D C.
Hybrid architecture for multiple transforms for signal processing applications Shikha Tripathi. - Bengaluru PES University 2018-2019
Realization of transforms such as N-point Discrete Fourier Transform (DFT), Discrete Cosine Transform (DCT), Discrete Sine Transform (DST) and Discrete Wavelet Transforms (DWT) has been implemented using a hybrid architecture. By decomposing N into smaller lengths, the transform algorithms are represented in triple-matrix-product form. The triplematrix-product form can be mapped onto a 2D systolic array. A controller is designed which can perform different transforms using the hybrid architecture based on the input provided to the controller. The implemented systolic array can be used for computing the diagonal elements of triple-matrix product. The implemented architecture produces the output of transform sequence in order, which avoids reordering at output. The implemented architecture can be used to handle large sized transforms by repeatedly using fixed size architecture for a large number of points without increasing the number of PEs. There is limited work reported on eff
Hybrid architecture for multiple transforms for signal processing applications Shikha Tripathi. - Bengaluru PES University 2018-2019
Realization of transforms such as N-point Discrete Fourier Transform (DFT), Discrete Cosine Transform (DCT), Discrete Sine Transform (DST) and Discrete Wavelet Transforms (DWT) has been implemented using a hybrid architecture. By decomposing N into smaller lengths, the transform algorithms are represented in triple-matrix-product form. The triplematrix-product form can be mapped onto a 2D systolic array. A controller is designed which can perform different transforms using the hybrid architecture based on the input provided to the controller. The implemented systolic array can be used for computing the diagonal elements of triple-matrix product. The implemented architecture produces the output of transform sequence in order, which avoids reordering at output. The implemented architecture can be used to handle large sized transforms by repeatedly using fixed size architecture for a large number of points without increasing the number of PEs. There is limited work reported on eff