Performance Trade-Off In Decision Diagram Based Synthesis Of Reversible Logic Circuits (Record no. 233607)

MARC details
000 -LEADER
fixed length control field 00890nam a2200145Ia 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 231221s9999 xx 000 0 und d
041 ## - LANGUAGE CODE
Language code of text/sound track or separate title English
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number CPEC15-1082
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Jayashree, H V. Anmol Prakash Surhonne. Agrawal, V K.
245 #0 - TITLE STATEMENT
Title Performance Trade-Off In Decision Diagram Based Synthesis Of Reversible Logic Circuits
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Date of publication, distribution, etc. 2015
500 ## - GENERAL NOTE
General note Performance Trade-Off In Decision Diagram Based Synthesis Of Reversible Logic Circuits Jayashree HV, Anmol Prakash Surhonne,V K Agrawal Dept. of Electronics and Communication, PES Institute of Technology,Bangalore. Email: jayashreehv@pes.edu, anmolpsuro@gmail.com, vk.agrawal@pes.edu IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 209-212. IEEE, 2015.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Performance,Trade-Off,Decision,Reversible,Logic,Circuits
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Institutional repository
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26/01/2024   CPEC15-1082 IR1082 26/01/2024 Institutional repository     EC   Central Library Central Library Central Library   EC RS 1    

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