A Further Optimized Mix Column Architecture Design for the Advanced Encryption Standard (Record no. 236116)

MARC details
000 -LEADER
fixed length control field 01282nam a2200133Ia 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 231221s9999 xx 000 0 und d
041 ## - LANGUAGE CODE
Language code of text/sound track or separate title English
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number CPEC19-1787
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Sudhir Rao Rupanagudi. Valliveti Vidya J. Varsha G Bhat. P Padmavathi. G Darshan. Nivedita Sindhu. Shreya K. Gurikar.
245 #2 - TITLE STATEMENT
Title A Further Optimized Mix Column Architecture Design for the Advanced Encryption Standard
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Date of publication, distribution, etc. 2019
510 ## - CITATION/REFERENCES NOTE
Name of source With the evolution of The Internet, there has been a huge spurt in online transactions and also an increase in sharing of private, confidential and sensitive information over the web. This in turn has increased the requirement of highly secure and swift methodologies to protect such data using modern cryptographic techniques such as the Advanced Encryption Standard (AES). In order to achieve the same, this paper discusses significant and novel modifications to the existing hardware architecture of the mix column step of the AES algorithm. By adopting these techniques, a speed efficiency of over 1.41 times was achieved as compared to previous algorithms. Moreover, in a VLSI perspective, an average area optimization of 3 times was also achieved. All experiments were conducted using the Xilinx Artix-7 series of FPGA.
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Institutional repository
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Date last seen Total checkouts Full call number Accession number Uniform resource identifier Price effective from Category Lost status Damaged status Withdrawn status Home library Current library Shelving location Entry date Grants Currency symbol Conversion rate Discount
26/01/2024   CPEC19-1787 IR1787 https://ieeexplore.ieee.org/document/8687545 26/01/2024 Institutional repository       Central Library Central Library Central Library   EC RS 1  

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