Normal view MARC view ISBD view

Design of High Speed Adders Using CMOS and Transmission Gates in Submicron Technology: A Comparative Study

By:

Material type:

TextLanguage: English Publication details: 2011 IEEE Port LouisSubject(s):

DDC classification:

Tags from this library: No tags from this library for this title. Log in to add tags.

Average rating: 0.0 (0 votes)

Holdings
Item type	Current library	Collection	Call number	Status	Barcode
Institutional repository	Central Library Central Library	EC	CPEC11-605 (Browse shelf(Opens below))	Available	IR605

Previous	No cover image available	No cover image available	No cover image available	No cover image available	No cover image available	No cover image available	No cover image available	Next
Previous	CPEC11-601 Efficient design and FPGA implementation of JPEG encoder using verilog HDL	CPEC11-603 Design and Implementation of a Linear Transconductance Amplifier with a Digitally Controlled Current Source	CPEC11-604 Simulated propagation through leafy vegetation	CPEC11-605 Design of High Speed Adders Using CMOS and Transmission Gates in Submicron Technology: A Comparative Study	CPEC11-607 Analysis of seasonal wind speed and wind power density distribution in Aimangala wind form at Chitradurga Karnataka using two parameter weibull distribution function	CPEC12-354 Different approaches of Designing an E-nose	CPEC12-357 Hardware implementation of voice operated robot using support vector machine classifier	Next

There are no comments on this title.

to post a comment.