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FPGA Implementation Of A Multilayer Artificial Neural Network Using System-On-Chip Design Methodology

By:

Ravikant G Biradar. Abhishek Chatterjee. Prabhakar Mishra. Koshy George

Material type:

TextLanguage: English Publication details: 2015Subject(s):

FPGA,Multilayer,Artificial,Neural,Network,Using,System-On-Chip,Methodology

DDC classification:

CPEC15-1047

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Holdings
Item type	Current library	Collection	Call number	Status	Barcode
Institutional repository	Central Library Central Library	EC	CPEC15-1047 (Browse shelf(Opens below))	Available	IR1047

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Previous	CPEC14-1367 Power Aware Fault Tolerance In Wireless Networks With Heterogeneous Nodes	CPEC15-1045 Design Of Priority Encoding Based Reversible Comparators	CPEC15-1046 Quantum Cost Realization Of New Reversible Gates With Transformation Based Synthesis Technique	CPEC15-1047 FPGA Implementation Of A Multilayer Artificial Neural Network Using System-On-Chip Design Methodology	CPEC15-1048 Implementation Of Efficient Serial-Parallel Decoder Architecture For Ieee 802.11ad Ldpc Code	CPEC15-1049 Design And Implementation Of Convolution Interleaver	CPEC15-1050 Text Line Segmentation Using Vector Quantization Incorporated Cluster Density Analysis	Next

FPGA Implementation of a Multilayer Artificial Neural Network using System-on-Chip Design Methodology International Conference on Cognitive Computing and Information Processing (CCIP 2015), , JSSATE, Noida, India, 3-4 March 2015

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