Design Of Optimized Reversible Multiplier For High Speed Dsp Application

By: Material type: TextLanguage: English Publication details: 2015Subject(s): DDC classification:
  • CPEC15-1083
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Design Of Optimized Reversible Multiplier For High Speed Dsp Application A N Nagamani1, Vishnu Shivakumar2, Rajendra Hathwar3, Vinod Kumar Agrawal4 1,2,3Department of Electronics and Communication Engineering, PES Institute of Technology, Bangalore, INDIA 4Director CORI, Professor , Department of Information Science and engineering, PES Institute of Technology, Bangalore, INDIA Email id: nagamani@pes.edu1, vishnuprasadstar@gmail.com2 , rajendra.hathwar18@gmail.com3 vk.agrawal@pes.edu4 2015 10th International Conference on, Information, Communications and Signal Processing (ICICS), pp. 1-5, IEEE, December 2015

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