Design And Implementation Of Reconfigurable Coders For Communication Systems Manikandan J, Shruthi S, Mangala SJ and Agrawal VK Department of Telecommunication, PES Institute of Technology, Bangalore Crucible of Research and Innovation (CORI), PES University, Bangalore Department of Electronics and Communication Engineering, PES University, Bangalore Email: manikandanj@pes.edu 2nd IEEE Int. Conf. on VLSI Systems, Architecture, Technology and Applications, Bangalore, pp.1-5, 10 - 12 January 2016

In this paper, a novel attempt is made to design a reconfigurable coder system which can be reconfigured on-the-fly to work either as an encoder, or decoder, or both encoder and decoder depending on the user requirements. In order to build the proposed reconfigurable system, Convolutional encoder, Viterbi decoder, Golay encoder and Golay decoder are employed in different combinations for the proposed design. The proposed system is implemented on a Virtex-5 FPGA and the performance of the system with and without reconfigurable architecture are reported. It is observed that 56.36% of hardware resources and 72.21% of power are saved on using reconfigurable architecture over non-reconfigurable architecture. The proposed system can be easily extended to include various other encoding and decoding schemes.