TY  - BOOK
AU  - Jayashree, H V. Anmol Prakash Surhonne. Agrawal, V K.
TI  - Performance Trade-Off In Decision Diagram Based Synthesis Of Reversible Logic Circuits
U1  - CPEC15-1082 
PY  - 2015///
KW  - Performance,Trade-Off,Decision,Reversible,Logic,Circuits
N1  - Performance Trade-Off In Decision Diagram Based Synthesis Of Reversible Logic Circuits Jayashree HV, Anmol Prakash Surhonne,V K Agrawal Dept. of Electronics and Communication, PES Institute of Technology,Bangalore. Email: jayashreehv@pes.edu, anmolpsuro@gmail.com, vk.agrawal@pes.edu  IEEE International Conference on Electron Devices and Solid-State Circuits                                (EDSSC), pp. 209-212. IEEE,  2015
ER  -