01282nam a2200133Ia 4500 231221s9999 xx 000 0 und d English CPEC19-1787 Sudhir Rao Rupanagudi. Valliveti Vidya J. Varsha G Bhat. P Padmavathi. G Darshan. Nivedita Sindhu. Shreya K. Gurikar. A Further Optimized Mix Column Architecture Design for the Advanced Encryption Standard 2019 With the evolution of The Internet, there has been a huge spurt in online transactions and also an increase in sharing of private, confidential and sensitive information over the web. This in turn has increased the requirement of highly secure and swift methodologies to protect such data using modern cryptographic techniques such as the Advanced Encryption Standard (AES). In order to achieve the same, this paper discusses significant and novel modifications to the existing hardware architecture of the mix column step of the AES algorithm. By adopting these techniques, a speed efficiency of over 1.41 times was achieved as compared to previous algorithms. Moreover, in a VLSI perspective, an average area optimization of 3 times was also achieved. All experiments were conducted using the Xilinx Artix-7 series of FPGA. IR 236116 236116 2024-01-26 00:00:00 0 CPEC19-1787 IR1787 https://ieeexplore.ieee.org/document/8687545 2024-01-26 IR 0 0 0 0 ML ML CL 0000-00-00 EC RS 1 0