01454nam a2200145Ia 4500008004100000041001200041082001600053100012200069245009200191260000900283510083000292942000701122999001901129952016001148231221s9999    xx            000 0 und d  aEnglish  aCPEC19-1787  aSudhir Rao Rupanagudi. Valliveti Vidya J. Varsha G Bhat. P Padmavathi. G Darshan. Nivedita Sindhu. Shreya K. Gurikar. 2aA Further Optimized Mix Column Architecture Design for the Advanced Encryption Standard  c2019  aWith the evolution of The Internet, there has been a huge spurt in online transactions and also an increase in sharing of private, confidential and sensitive information over the web. This in turn has increased the requirement of highly secure and swift methodologies to protect such data using modern cryptographic techniques such as the Advanced Encryption Standard (AES). In order to achieve the same, this paper discusses significant and novel modifications to the existing hardware architecture of the mix column step of the AES algorithm. By adopting these techniques, a speed efficiency of over 1.41 times was achieved as compared to previous algorithms. Moreover, in a VLSI perspective, an average area optimization of 3 times was also achieved. All experiments were conducted using the Xilinx Artix-7 series of FPGA.  cIR  c236116d236116  r2024-01-26 00:00:00l0oCPEC19-1787pIR1787uhttps://ieeexplore.ieee.org/document/8687545w2024-01-26yIR10407000aMLbMLcCLd0000-00-00EECGRSF1V0