Nivedita, S. <br/><br/>
Design for Debug & Logic Verification for Type C USB  Shikha Tripathi. 

 - Bengaluru  PES University  2018-2019 
<br/><br/> Verification is done to evaluate whether or not a product, service, or system complies with a regulation, requirement, specification, or imposed condition. It is often an internal process. It is a process in which a design is tested against a given design specification before tape-out. It is in contrast with validation. With increasing years, tremendous progress has been seen in VLSI technology which is enabling the integration of many millions of transistors into just a single chip in order to make a SoC (System-on-Chip). Also we can say that due to advancement in VLSI technology the complexity of System on Chip (SoC) design have been increased. The System Verilog language became a solution to many verification engineers. With special features like classes, cover groups and constraints that has made verification of digital design easier verification methodologies gained momentum. Mixed-signal design is becoming more and more popular and also useful nowadays because the des