000			00557nam a2200145Ia 4500
008			231221s9999 xx 000 0 und d
020			_a978-0-387-48550-8
041			_aEnglish
100			_aPrashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar
245		0	_aRouting Congestion in VLSI Circuits: Estimation and Optimization
260			_c2007 _bSpringer US _aNew York
440			_aIntegrated Circuits and Systems
650			_aCircuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Communications Engineering, Networks
942			_cEB
999			_c225666 _d225666