| 000 | 00890nam a2200145Ia 4500 | ||
|---|---|---|---|
| 008 | 231221s9999 xx 000 0 und d | ||
| 041 | _aEnglish | ||
| 082 | _aCPEC15-1082 | ||
| 100 | _aJayashree, H V. Anmol Prakash Surhonne. Agrawal, V K. | ||
| 245 | 0 | _aPerformance Trade-Off In Decision Diagram Based Synthesis Of Reversible Logic Circuits | |
| 260 | _c2015 | ||
| 500 | _aPerformance Trade-Off In Decision Diagram Based Synthesis Of Reversible Logic Circuits Jayashree HV, Anmol Prakash Surhonne,V K Agrawal Dept. of Electronics and Communication, PES Institute of Technology,Bangalore. Email: jayashreehv@pes.edu, anmolpsuro@gmail.com, vk.agrawal@pes.edu IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 209-212. IEEE, 2015. | ||
| 650 | _aPerformance,Trade-Off,Decision,Reversible,Logic,Circuits | ||
| 942 | _cIR | ||
| 999 |
_c233607 _d233607 |
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