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041			_aEnglish
082			_aCPEC19-1787
100			_aSudhir Rao Rupanagudi. Valliveti Vidya J. Varsha G Bhat. P Padmavathi. G Darshan. Nivedita Sindhu. Shreya K. Gurikar.
245		2	_aA Further Optimized Mix Column Architecture Design for the Advanced Encryption Standard
260			_c2019
510			_aWith the evolution of The Internet, there has been a huge spurt in online transactions and also an increase in sharing of private, confidential and sensitive information over the web. This in turn has increased the requirement of highly secure and swift methodologies to protect such data using modern cryptographic techniques such as the Advanced Encryption Standard (AES). In order to achieve the same, this paper discusses significant and novel modifications to the existing hardware architecture of the mix column step of the AES algorithm. By adopting these techniques, a speed efficiency of over 1.41 times was achieved as compared to previous algorithms. Moreover, in a VLSI perspective, an average area optimization of 3 times was also achieved. All experiments were conducted using the Xilinx Artix-7 series of FPGA.
942			_cIR
999			_c236116 _d236116