Performance Trade-Off In Decision Diagram Based Synthesis Of Reversible Logic Circuits
Material type:
TextLanguage: English Publication details: 2015Subject(s): DDC classification: - CPEC15-1082
| Item type | Current library | Collection | Call number | Status | Barcode | |
|---|---|---|---|---|---|---|
| Institutional repository | Central Library Central Library | EC | CPEC15-1082 (Browse shelf(Opens below)) | Available | IR1082 |
Performance Trade-Off In Decision Diagram Based Synthesis Of Reversible Logic Circuits Jayashree HV, Anmol Prakash Surhonne,V K Agrawal Dept. of Electronics and Communication, PES Institute of Technology,Bangalore. Email: jayashreehv@pes.edu, anmolpsuro@gmail.com, vk.agrawal@pes.edu IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 209-212. IEEE, 2015.
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